The present invention relates to an LSI memory having a reduced number of address input lines.
The memory capacity of LSIs has greatly increased together with development of LSI techniques. The number of address lines for accessing a memory address and the package size for memory elements thereof have also increased. Static RAM and ROM are typical examples. FIG. 1A shows a conventional LSI memory of this type. For example, a 512k-bit static RAM 1 is connected to 16 address input lines 2 and an 8-bit data output bus 3.
A large number of memory chips are used to form an LSI memory. However, an address signal is supplied thereto in a time-division manner, thereby limiting the package size. A typical example is a dynamic RAM, as shown in FIG. 1B. A 64k-bit dynamic RAM 4 is connected to 16 address input lines 5, a 16-bit data output bus, a 16-out-of-8 selector (16 input lines and 8 output lines) 7 and eight address input lines 8. In this case, the address selector 7 must be arranged outside the LSI memory 4. This means that not much can be expected from an LSI memory having a small memory capacity. The overall hardware size and access time are thus increased, resulting in inconvenience.